Huge Memory Bandwidth, but not for every Block

One highly intriguing aspect of the M1 Max, maybe less so for the M1 Pro, is the massive memory bandwidth that is available for the SoC.

Apple was keen to market their 400GB/s figure during the launch, but this number is so wild and out there that there’s just a lot of questions left open as to how the chip is able to take advantage of this kind of bandwidth, so it’s one of the first things to investigate.

Starting off with our memory latency tests, the new M1 Max changes system memory behaviour quite significantly compared to what we’ve seen on the M1. On the core and L2 side of things, there haven’t been any changes and we consequently don’t see much alterations in terms of the results – it’s still a 3.2GHz peak core with 128KB of L1D at 3 cycles load-load latencies, and a 12MB L2 cache.

Where things are quite different is when we enter the system cache, instead of 8MB, on the M1 Max it’s now 48MB large, and also a lot more noticeable in the latency graph. While being much larger, it’s also evidently slower than the M1 SLC – the exact figures here depend on access pattern, but even the linear chain access shows that data has to travel a longer distance than the M1 and corresponding A-chips.

DRAM latency, even though on paper is faster for the M1 Max in terms of frequency on bandwidth, goes up this generation. At a 128MB comparable test depth, the new chip is roughly 15ns slower. The larger SLCs, more complex chip fabric, as well as possible worse timings on the part of the new LPDDR5 memory all could add to the regression we’re seeing here. In practical terms, because the SLC is so much bigger this generation, workloads latencies should still be lower for the M1 Max due to the higher cache hit rates, so performance shouldn’t regress.

A lot of people in the HPC audience were extremely intrigued to see a chip with such massive bandwidth – not because they care about GPU or other offload engines of the SoC, but because the possibility of the CPUs being able to have access to such immense bandwidth, something that otherwise is only possible to achieve on larger server-class CPUs that cost a multitude of what the new MacBook Pros are sold at. It was also one of the first things I tested out – to see exactly just how much bandwidth the CPU cores have access to.

Unfortunately, the news here isn’t the best case-scenario that we hoped for, as the M1 Max isn’t able to fully saturate the SoC bandwidth from just the CPU side;

From a single core perspective, meaning from a single software thread, things are quite impressive for the chip, as it’s able to stress the memory fabric to up to 102GB/s. This is extremely impressive and outperforms any other design in the industry by multiple factors, we had already noted that the M1 chip was able to fully saturate its memory bandwidth with a single core and that the bottleneck had been on the DRAM itself. On the M1 Max, it seems that we’re hitting the limit of what a core can do – or more precisely, a limit to what the CPU cluster can do.

The little hump between 12MB and 64MB should be the SLC of 48MB in size, the reduction in BW at the 12MB figure signals that the core is somehow limited in bandwidth when evicting cache lines back to the upper memory system. Our test here consists of reading, modifying, and writing back cache lines, with a 1:1 R/W ratio.

Going from 1 core/threads to 2, what the system is actually doing is spreading the workload across the two performance clusters of the SoC, so both threads are on their own cluster and have full access to the 12MB of L2. The “hump” after 12MB reduces in size, ending earlier now at +24MB, which makes sense as the 48MB SLC is now shared amongst two cores. Bandwidth here increases to 186GB/s.

Adding a third thread there’s a bit of an imbalance across the clusters, DRAM bandwidth goes to 204GB/s, but a fourth thread lands us at 224GB/s and this appears to be the limit on the SoC fabric that the CPUs are able to achieve, as adding additional cores and threads beyond this point does not increase the bandwidth to DRAM at all. It’s only when the E-cores, which are in their own cluster, are added in, when the bandwidth is able to jump up again, to a maximum of 243GB/s.

While 243GB/s is massive, and overshadows any other design in the industry, it’s still quite far from the 409GB/s the chip is capable of. More importantly for the M1 Max, it’s only slightly higher than the 204GB/s limit of the M1 Pro, so from a CPU-only workload perspective, it doesn’t appear to make sense to get the Max if one is focused just on CPU bandwidth.

That begs the question, why does the M1 Max have such massive bandwidth? The GPU naturally comes to mind, however in my testing, I’ve had extreme trouble to find workloads that would stress the GPU sufficiently to take advantage of the available bandwidth. Granted, this is also an issue of lacking workloads, but for actual 3D rendering and benchmarks, I haven’t seen the GPU use more than 90GB/s (measured via system performance counters). While I’m sure there’s some productivity workload out there where the GPU is able to stretch its legs, we haven’t been able to identify them yet.

That leaves everything else which is on the SoC, media engine, NPU, and just workloads that would simply stress all parts of the chip at the same time. The new media engine on the M1 Pro and Max are now able to decode and encode ProRes RAW formats, the above clip is a 5K 12bit sample with a bitrate of 1.59Gbps, and the M1 Max is not only able to play it back in real-time, it’s able to do it at multiple times the speed, with seamless immediate seeking. Doing the same thing on my 5900X machine results in single-digit frames. The SoC DRAM bandwidth while seeking around was at around 40-50GB/s – I imagine that workloads that stress CPU, GPU, media engines all at the same time would be able to take advantage of the full system memory bandwidth, and allow the M1 Max to stretch its legs and differentiate itself more from the M1 Pro and other systems.

M1 Pro & M1 Max: Performance Laptop Chips Power Behaviour: No Real TDP, but Wide Range
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  • ruthan - Friday, October 29, 2021 - link

    So great on paper and for some number crunching, compiling and maybe some video editing.. but where you really need performance for gaming it sucks... and all Apples lofty paper specs are gone. I know that there is some translation layer, but its Apple choice to use it.
  • richardnpaul - Sunday, October 31, 2021 - link

    I think that that is a bit of an unfair characterisation at this stage.
  • jojo62 - Saturday, October 30, 2021 - link

    I am programmer. Not a gaming programmer but I use my Mac Book Pro 2019 to connect to my work computer. I run Databases like Oracle 21c, microsoft sql server, and others in Windows 11 on my Mac. The performance is great and these laptops last forever. I still have my mac book pro 2012 laptop and it works. I've had many many computers over the years and they all seem to die after 3-4 years but not my apple computers. I think PC makers have implemented planned Obsolescence on their products. I am upgrading to the new mac book pro m1 max soon.
  • razer555 - Saturday, October 30, 2021 - link

    Anadtech, It seems you really need to test with Baldur's gate 3 which can perform 4K 100~120 FPS.
  • ailooped - Monday, November 1, 2021 - link

    What 7? years back there were proof of concept ARM computers that proved you can run many many processors in parallel. I am not that technically apt, of course. However this seems like apple taking advantage of that fact.

    They are just doubling everything. I am guessing we will see a 64 core graphics and perhaps a max of 128 core for Mac Pro. With M2 cpu cores also doubling to 24 cores or something like that.

    Yes, Apple chose to say goodbye to windows compatibility. However, they have a HUGE developer base in iOS. And they (Mac and iOS) are now on-par and running on the same silicone.

    This is a disruption to the pc world no matter how you slice it. Of course, intel can see it hence the smear ads against apple. Windows is quietly tinkering with their ARM version of windows, just to see if apple can actually take off with it.

    The pc ecosystem is already suffering from the influx of powerful smartphones/tablets. And now apple is in 100% with ARM computers, with a HUGE iOS user base what will be seduced by a seamless transition to Macs from iPhones? Perhaps.. Understandable that Apple is trying...

    Do you really mind though? The Intel/AMD/Nvidia trifecta seems to be quite stagnant on CISC. Perhaps it`s better for the PC ecosystem to be on the same silicone as phones and tablets... To benefit from ALL that R&D money going into it...
  • ailooped - Monday, November 1, 2021 - link

  • ailooped - Monday, November 1, 2021 - link

    To be quite honest, I am not sure I want to see Apple with their approach to hardware gain tons of marketshare on the desktop/laptops.. No upgradeability... RAM integrated into CPU... I DO however think Intel/AMD/Nvidia can do with a fourth player in the GPU/CPU game..
  • jmmx - Tuesday, November 2, 2021 - link

    It would be nice to see some discussion of the NPU. I imagine it would be hard to find any tests across platforms but some type of evaluation would be helpful.
  • bgnn - Tuesday, November 2, 2021 - link

    Clarification on node advantage.. I've designed in both 7nm and 5nm. The power and performance increases are marginal compared to good old days. Back then when we switched from 32nm to 28nm we had more than 70% perf/power increase. 7nm to 5nm it's more like 25% at best. Density is the main benefit. Interconnect is killing it for smaller nodes. Gate contacts are tiny and they are incredibly resistive..
  • Hrunga_Zmuda - Sunday, November 7, 2021 - link

    Anyone who actually designs in this corner of the computer industry must be familiar with the law of diminishing returns. Right?

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